1. Field of the Invention
Embodiments of the present invention generally relate to methods for forming semiconductor devices. More particularly, embodiments of the present invention generally relate to methods for pre-cleaning metal contacts on a semiconductor substrate.
2. Description of the Related Art
Metal gates or contacts typically include a doped silicon surface, one or more barrier layers, one or more liner layers and bulk metal to complete the gate structure. The cleanliness of the substrate surface between layers is critical for reducing contact resistance and hence, optimal device performance. For logic devices, the contact is usually a silicide, such as nickel silicide, cobalt silicide, or titanium silicide. Nickel silicide is becoming more popular for smaller geometries, e.g., geometries having aspect ratios of about 10:1 or smaller, because nickel silicide is widely available and has a lower resistivity and lower contact resistance as compared to other metal silicides.
In a typical fabrication process, the metal silicide is formed on a substrate in one vacuum environment and the substrate is then transferred to another vacuum environment to continue the contact interconnection manufacturing process. As a result, the substrate can be subjected to oxidative conditions during the transfer. A clean process is typically conducted prior to the liner/barrier deposition to remove any oxides on the silicide surface which formed during transfer and exposure to the oxidative environment.
FIGS. 1A-1C depicts cross-sectional views of a localized contact structure in a semiconductor device. Typically, a contact structure 100 includes a substrate 102 having a gate structure 108 formed on the substrate 102, as shown in FIG. 1A. Source and drain regions 106, 104 are formed in the substrate 102 adjacent to the gas structure 108. The gate structure 108 includes a gate dielectric 112, a gate electrode 122 and a contact layer 110. The contact layer 110 is also formed in the source 106 and the drain 104 region. The contact layer 110 may be a metal silicide, a silicon based material, a germanium based material, or a silicon based material doped with germanium and/or other dopant. An etch stop layer 116 is formed on the substrate 102 covering the gate structure 108. The etch stop layer 116 is typically made by a silicon dielectric layer, such as a SiN layer. A contact dielectric layer 118 is then deposited over the substrate 102.
FIG. 2 depicts a flow chart conventionally utilized to manufacture a contact structure 100 depicted in FIGS. 1A-1C. When manufacturing the contact structure 100, a contact etching process is performed to etch the contact dielectric layer 118 and the etch stop layer 116 so as to form vias/trenches 120, as shown in FIG. 1B, in the contact dielectric layer 118 and the etch stop layer 116, as described at step 202 in FIG. 2. It is noted that conventionally, the dielectric layer 118 and the etch stop layer 116 individually are etched in separate steps. After the etching process, a top surface 150 and an upper surface 152 of the contact layer 110 are exposed, as shown in FIG. 1B. At step 204, conventionally, a wet cleaning process is performed to remove etching residuals that may remain on the top surface 150 of the contact layer 110 and the upper surface 152 of the substrate 102. After the wet cleaning process, at step 206, a pre-clean process is performed to remove native oxides formed on the top surface 150 of the contact layer 110, sidewalls 154 of the contact dielectric layer 118 and the upper surface 152 of the contact layer 110. Native oxides may adversely increase contact resistance of the device structure, thereby undesirably resulting in poor electrical performance and device failure. After the pre-clean process, a metallization process, including forming of the barrier layer and the contact metal plug layer 124, is performed at step 208, to complete the metal contact structure formation process, as shown in FIG. 1C.
As discussed above, conventional pre-clean processes utilize physical etch techniques, e.g., sputtering. Sputtering techniques can damage the underlying surface due to resputtering of oxide onto the silicide surface. Sputtering techniques can also change the contact hole geometry due to the physical bombardment of ions on the substrate surface. For example, the contact opening can become widened or tapered which is sometimes referred to as “faceting” due to the nature of the isotropic etch of the physical etch techniques, thereby resulting in critical dimension (CD) widening or enlargement.
Furthermore, substrate transfer between different processing chambers to perform the etch stop layer etching processing, wet cleaning process, and the pre-cleaning process for native oxide removal may expose the substrate to ambient atmosphere, which may adversely increase likelihood of re-growing native oxides and be the source of other contaminates formed on the substrate surface.
Therefore, there is a need for an improved pre-clean process for cleaning the metal gates prior to the contact metallization process.